Conventionally, switching power supplies using switching control circuits are widely used as power supplies for supplying power to kinds of electronic equipment for home use and industrial use. Further, LED drivers using switching control circuits are conventionally proposed as LED drivers. The following will describe conventional switching control circuits used for switching power supplies and LED drivers.
FIGS. 10A and 10B are block diagrams schematically showing the conventional switching control circuits. In FIGS. 10A and 10B, reference numeral 1 denotes an inductive load, reference numeral 2 denotes a switching element, reference numeral 3 denotes a control circuit, reference numeral 4 denotes a power supply, reference numeral 5 denotes a current detection circuit, reference numeral 6 denotes an on/off circuit, reference numeral 8 denotes a drain current detection circuit, reference numeral 9 denotes an on-period blanking pulse generator circuit, and reference numeral 10 denotes an AND circuit.
The switching control circuit of FIG. 10A includes the switching element 2 having a high potential terminal connected to the inductive load 1 and a low potential terminal connected to a circuit reference potential, the control circuit 3 for controlling the periodic on/off operation of the switching element 2, and the power supply 4 for the control circuit 3. The control circuit 3 includes the current detection circuit 5 for detecting drain current IDS passing through the switching element 2 and the on/off circuit 6. The current detection circuit 5 includes the drain current detection circuit 8, the on-period blanking pulse generator circuit 9, and the AND circuit 10.
The on/off circuit 6 generates a gate signal with a fixed oscillation frequency, applies the gate signal to the control terminal of the switching element 2, and controls the periodic on/off operation of the switching element 2. To be specific, the on/off circuit 6 performs PWM control according to a peak current control scheme based on an output signal OC of the current detection circuit 5. The output signal OC determines the turn-off of the switching element 2. Further, the on/off circuit 6 starts at the rising edge of the gate signal and generates a control signal PULSE whose pulse width is the maximum on period Tonmax of the switching element 2.
The drain current detection circuit 8 connected to the high potential terminal of the switching element 2 detects the drain current IDS according to a detection criterion which can be arbitrarily set or adjusted, and the drain current detection circuit 8 generates an element current detection signal OC_D for turning off the switching element 2. To be specific, when the current value of the drain current IDS is equal to or exceeds the detection criterion specified in the drain current detection circuit 8, the drain current detection circuit 8 sets the element current detection signal OC_D at a high level. The following will describe the case where the drain current detection circuit 8 sets, when the current value of the drain current IDS is equal to or higher than the detection criterion, the element current detection signal OC_D at a high level.
The on-period blanking pulse generator circuit 9 generates, based on the gate signal of the on/off circuit 6, a blanking pulse signal BLK for making the element current detection signal OC_D ineffective for a fixed period (blanking period Tblk) after a transition of the switching element 2 from off state to on state.
The AND circuit 10 ANDs the element current detection signal OC_D from the drain current detection circuit 8 and the blanking pulse signal BLK from the on-period blanking pulse generator circuit 9, and sets the output signal OC at a high level when the signals are both set at a high level.
As described above, the current detection circuit 5 sets the output signal OC at a high level after the lapse of the blanking period Tblk since the switching element 2 is turned on. Therefore, the current detection circuit 5 does not detect capacitive spike noise occurring during the transition of the switching element 2 from off state to on state. Thus the conventional switching control circuit can prevent the switching element 2 from being turned off (malfunction) by the detection of capacitive spike noise.
The switching control circuit of FIG. 10B is identical in configuration to the switching control circuit of FIG. 10A except for a different connection of the detection terminal of the drain current detection circuit 8. The operations of the switching control circuit of FIG. 10B are the same as those of the switching control circuit of FIG. 10A. The following explanation will be given based on the switching control circuit of FIG. 10A.
As described above, the conventional switching control circuit performs PWM control (fixed oscillation frequency) according to a peak current control scheme (for example, Japanese Patent Laid-Open No. 5-276761, Japanese Patent Laid-Open No. 2004-208382, Japanese Patent Laid-Open No. 2004-336860).
However, the conventional switching control circuit has the following problems:
The problems of the conventional switching control circuit will be discussed below with reference to FIGS. 11A, 11B, and 11C which are the operation waveform charts of the conventional switching control circuit. In the conventional switching control circuit, PWM control on the switching element 2 has three states shown in FIGS. 11A, 11B, and 11C.
In FIGS. 11A, 11B, and 11C, Tblk represents a blanking period and Toc represents a detection delay period. The detection delay period is a period from when the drain current detection circuit 8 detects that the drain current IDS is equal to or higher than the detection criterion to when the switching element 2 is actually turned off. Thus the switching element 2 is turned off with a delay of a predetermined period in response to the gate signal generated by the on/off circuit 6.
In FIGS. 11A, 11B, and 11C, PULSE represents the control signal generated in the on/off circuit 6, OC_D represents the element current detection signal generated by the drain current detection circuit 8, OC represents the output signal of the current detection circuit 5, the output signal being generated by the AND circuit 10, BLK represents the blanking pulse signal generated by the on-period blanking pulse generator circuit 9, GATE represents the gate voltage of the switching element 2, IDS represents the drain current passing through the switching element 2, IDSmax represents the maximum value of the drain current IDS specified according to the detection criterion in the drain current detection circuit 8, and IDSmin represents the minimum value of the drain current IDS specified according to the detection criterion in the drain current detection circuit 8.
FIG. 11A shows the switching element 2 under PWM control in a steady state. In this case, the drain current IDS reaches the maximum value IDSmax according to the detection criterion in the drain current detection circuit 8.
FIG. 11B shows that the on period of the switching element 2 is equal to the sum of the blanking period Tblk and the detection delay period Toc (hereinafter, the sum of the blanking period Tblk and the detection delay period Toc will be referred to as the minimum pulse period). In this case, the drain current IDS reaches the minimum value IDSmin according to the detection criterion in the drain current detection circuit 8.
FIG. 11C shows that the on period of the switching element 2 is equal to the minimum pulse period and the drain current IDS largely exceeding the maximum value IDSmax passes during the on period. The drain current IDS largely exceeding the maximum value IDSmax passes because when the on period of the switching element 2 is equal to the minimum pulse period, the current detection circuit 5 does not detect the drain current IDS and the on/off circuit 6 cannot perform PWM control on the switching element 2.
As described above, in the conventional switching control circuit, when the on period of the switching element 2 is equal to the minimum pulse period, the drain current IDS largely exceeding the maximum value IDSmax may pass during the on period. Such excessive current passing through the switching element 2 may cause degradation (breakage in some cases) of the switching element 2.
The following will discuss a problem caused by the conventional switching control circuit used for, for example, a switching power supply shown in FIG. 12. In FIG. 12, reference numeral 11 denotes a snubber circuit, reference numeral 12 denotes a transformer, reference numeral 13 denotes a diode, and reference numeral 14 denotes a capacitor.
In the conventional switching power supply, the snubber circuit 11 and the primary side of the transformer 12 are connected to the conventional switching control circuit, and a rectifying/smoothing circuit made up of the diode 13 and the capacitor 14 is connected to the secondary side of the transformer 12. Output terminals OUTPUT and RETURN are connected to the capacitor 14.
Further, the conventional switching power supply includes an output voltage detection circuit (not shown) connected to the output terminal OUTPUT. The output voltage detection circuit detects the voltage of the output terminal OUTPUT and generates a detection signal for adjusting the detection criterion of the drain current detection circuit 8 according to the value of the detected voltage. PWM control on the switching element 2 is performed in response to the detection signal of the output voltage detection circuit.
In the conventional switching power supply, energy (power) generated on the secondary side of the transformer 12 is supplied to the diode 13 and the capacitor 14 in response to the switching operation (periodic on/off operation) of the switching element 2. The diode 13 and the capacitor 14 rectify and smooth the voltage from the transformer 12 to generate output voltage OUT, and output the output voltage OUT from the output terminal.
FIG. 13 shows the operation waveforms of the conventional switching power supply when terminal voltage VIN of an input terminal INPUT gradually increases, for example, immediately after power is turned on. In FIG. 13, VIN represents an input voltage inputted to the input terminal INPUT, OUT represents an output voltage outputted from the output terminal, and ID represents a secondary side current passing through the diode 13.
As shown in FIG. 13, when the terminal voltage (input voltage) VIN of the input terminal INPUT gradually increases, the switching element 2 is controlled in response to the control signal PULSE. The inclination of the drain current IDS passing through the switching element 2 (inclination after the passage of capacitive spike current) increases in proportion to the input voltage VIN. For this reason, in the switching power supply using the conventional switching control circuit, when the input voltage VIN gradually increases as shown in FIG. 13, the on period of the switching element 2 is equal to the minimum pulse period, PWM control on the switching element 2 is disabled, and the peak value of the drain current IDS increases every time the switching element 2 is periodically turned on/off. The peak value of the drain current IDS increases because when the switching element 2 is turned off, all energy accumulated in the transformer 12 remains as it is without being supplied to the diode 13 or the capacitor 14, and the energy increases every time the switching element 2 is periodically turned on/off. Such an increase in the peak value of the drain current IDS may cause degradation (breakage in some cases) of the switching element 2, so that the reliability and life of the switching power supply may be adversely affected.
The following will discuss a problem of the conventional switching control circuit used for, for example, an LED driver shown in FIG. 14. In FIG. 14, reference numeral 15 denotes an LED device and reference numeral 16 denotes a diode. The LED device 15 includes a protective device for improving surge tolerance. In the LED driver, the LED device 15 and the diode 16 are connected to the conventional switching control circuit. The conventional LED driver has an FB terminal. The detection criterion of the drain current IDS passing through the switching element 2 can be changed from the outside through the FB terminal.
FIG. 15 shows the operation waveforms of the conventional LED driver when the luminance of the LED is adjusted by gradually reducing the peak value of the drain current IDS passing through the switching element 2. In FIG. 15, VIN represents an input voltage inputted to the input terminal INPUT, VFB represents a terminal voltage of the FB terminal, and IL represents a current passing through the inductive load 1.
In the LED driver using the conventional switching control circuit, in order to gradually reduce, as indicated by reference numeral 17 in FIG. 15, the peak value of the drain current IDS passing through the switching element 2, the terminal voltage VFB is gradually reduced as shown FIG. 15 so as to gradually reduce the detection criterion. In this case, when the on period of the switching element 2 is equal to the minimum pulse period, the conventional LED driver cannot shorten the on period any more. Therefore in the conventional LED driver, the luminance of the LED cannot be set at a certain value or lower, so that the dimming range is reduced and poor dimming occurs.